In U.S. Pat. No. 4,085,644 there is described a Polyphonic Tone Synthesizer in which a master data set is computed and stored in a main register from which it is transferred to note registers of a plurality of tone generators. The master data set defines the amplitudes of equally spaced points along a half cycle of the audio waveform of the musical tones being generated. Each tone generator receives the words in the master data set and applies them to a digital-to-analog converter at a rate determined by the fundamental pitch of the respective tones being generated by the Polyphonic Tone Synthesizer.
One of the features of the Polyphonic Tone Synthesizer, as described in the above-identified patent, is that the transfer of successive words from the master data set in the main register to an individual note register in the respective tone generators is synchronized with the transfer of words from the note register to the digital-to-analog converter in the respective tone generators. This feature permits the master data set defining the waveform to be recomputed and loaded in the respective tone generators without interrupting the generation of the respective musical notes by the tone generators, thus permitting the waveform of a musical tone to be changed with time without interrupting the resulting musical tone.
The rate at which the waveform can be varied as a function of time is limited by the length of time required for a computation cycle during which the master data set is generated and the length of time required to transfer the data from the main register to the note registers in each of the tone generators. Methods for reducing the time required for the data transfer are described in the copending application Ser. No. 011,056 filed Feb. 9, 1979 entitled "Data Transfer Apparatus For Digital Polyphonic Tone Synthesizer."
An obvious method of reducing the time required for the computation cycle is to simply increase the frequency of the logic master clock which provides the timing signals for the system logic. There are practical as well as economic limitations imposed upon the speed, or frequency, of the master clock. If the Polyphonic Tone Synthesizer is implemented with large scale integrated microelectronics, then the present state-of-the-art limits the master clock to about 2 to 3 mhz. Since the cost of microelectronics rises very fast at the high end of the speed limits, it is desirable to achieve a decreased computation cycle time without increasing the speed of the master clock.
Methods for reducing the computation time are described in the copending application Ser. No. 28,038 filed Apr. 9, 1979 entitled "Even-Odd Symmetric Computation In A Polyphonic Tone Synthesizer." The computation time is reduced by computing a reduced size of the number of points in the master data set. The number of these points is 16 which is a reduction of one-fourth from the required number of 64 points for generating musical tones characterized by 32 harmonics. The reduction in the size of the master data set is accomplished by decomposing the master data set into two component subsets. The first component is generated using only the odd harmonic coefficients and the second component is generated using only the even harmonic coefficients. The component master data sets are stored in two memories. During the transfer cycle, the desired full cycle waveshape data is created by forward and backward addressing of the data stored in the two memories. The addressed data is complemented and added in a specified manner so that the desired full cycle waveshape is created from a total of 16 master data set points instead of using 64 data points as required by the note registers. In this fashion, the time required for the creation of the master data set during the computation cycle is reduced by a factor of four corresponding to the generation of only 16 data points instead of the nominal 64 data points.